III–V compound semiconductors for mass-produced nano-electronics: theoretical studies on mobility degradation by dislocation

As silicon-based electronics approach the limit of scaling for increasing the performance and chip density, III-V compound semiconductors have started to attract significant attention owing to their high carrier mobility. However, the mobility benefits of III-V compounds are too easily accepted, ignoring a harmful effect of unavoidable threading dislocations that could fundamentally limit the applicability of these materials in nanometer-scale electronics. In this paper, we present a theoretical model that describes the degradation of carrier mobility by charged dislocations in quantum-confined III-V semiconductor metal oxide field effect transistors (MOSFETs). Based on the results, we conclude that in order for III-V compound MOSFETs to outperform silicon MOSFETs, Fermi level pinning in the channel should be eliminated for yielding carriers with high injection velocity.